{ "warnings": [ "The single VCC pin must stay between 2.7 V and 5.5 V for the -20PU industrial variant (1.8-5.5 V for ATTINY85V low-voltage variants). Exceeding 6.0 V will damage the device.", "The 20 MHz speed grade only applies when VCC is between 4.5 V and 5.5 V. At 3.3 V the maximum reliable clock is 10 MHz.", "There is no hardware UART on the ATtiny85. UART communication must be bit-banged in firmware (e.g. via SoftwareSerial or Timer0 in CTC mode).", "Programming the RSTDISBL fuse to free PB5 as a GPIO permanently disables ISP programming; recovery requires a high-voltage serial programmer.", "The internal RC oscillator drifts with temperature and supply voltage; precision-timed protocols may require an external crystal or careful OSCCAL trimming." ], "domains": [ { "power_domains": [ { "voltage_range_V": [ 2.7, 5.5 ], "name": "Core/I-O supply", "id": "vcc", "isolation_type": "non_isolated", "nominal_voltage_V": 5, "description": "Single VCC rail supplies both the AVR core and the I/O pad ring. ATTINY85-20PU is rated 2.7-5.5 V for operation up to 10 MHz and 4.5-5.5 V for operation up to 20 MHz. Total continuous current through the VCC or GND pin is limited to 200 mA. Recommended 0.1 uF decoupling cap close to pin 8.", "ground_reference": "common", "max_current_mA": 200 } ], "pin_count": 20, "supply_voltage_V": [ 2.7, 5.5 ], "interfaces": [ { "description": "Single-rail DC supply input. 2.7-5.5 V (10 MHz max) or 4.5-5.5 V (20 MHz max). Place a 100 nF decoupling capacitor between VCC (pin 8) and GND (pin 4) close to the package.", "requires": [ { "count": 1, "function": "VCC" }, { "count": 1, "function": "GND" } ], "name": "VCC / GND", "id": "power_input", "constraints": { "requires_matching_voltage_domain": true, "max_connections": 1 }, "protocol": { "role": "input", "type": "power" } }, { "description": "USI bus", "requires": [ { "function": "USCK", "count": 1 }, { "count": 1, "function": "DO" }, { "function": "DI", "count": 1 } ], "protocol": { "role": [ "master", "slave", "clock_provider" ], "type": "usi" }, "name": "USI", "id": "usi" }, { "description": "I2C bus", "requires": [ { "count": 1, "function": "SDA" }, { "function": "SCL", "count": 1 } ], "protocol": { "role": [ "master", "slave" ], "type": "i2c" }, "name": "I2C", "id": "i2c" }, { "requires": [ { "function": "SCK", "count": 1 }, { "count": 1, "function": "MOSI" }, { "count": 1, "function": "MISO" } ], "protocol": { "role": [ "master", "slave", "clock_provider" ], "type": "spi" }, "name": "SPI", "id": "spi", "description": "SPI bus" }, { "description": "Comparator Positive (AIN0) and Negative (AIN1) Inputs", "requires": [ { "count": 1, "function": "AIN0" }, { "count": 1, "function": "AIN1" } ], "name": "Comparator", "id": "comparator", "protocol": { "role": [ "master" ], "type": "comparator" } }, { "name": "PWM", "id": "pwm", "protocol": { "role": [ "master" ], "type": "pwm" }, "requires": [ { "function": "PWM", "count": 1 } ], "description": "PWM outputs" }, { "description": "!PWM outputs", "requires": [ { "count": 1, "function": "!PWM" } ], "name": "!PWM", "id": "not_pwm", "protocol": { "role": [ "master" ], "type": "pwm" } }, { "name": "ADC", "id": "adc", "protocol": { "role": [ "master" ], "type": "adc" }, "requires": [ { "count": 1, "function": "ADC" } ], "description": "Analog-to-Digital Converter" }, { "description": "Pin change interrupt capability", "name": "Pin Change Interrupt", "id": "pin_change_interrupt", "protocol": { "role": [ "master" ], "type": "pin_change_interrupt" }, "requires": [ { "function": "Pin Change Interrupt", "count": 1 } ] }, { "name": "Interrupt", "id": "interrupt", "protocol": { "role": [ "master" ], "type": "interrupt" }, "requires": [ { "function": "Interrupt", "count": 1 } ], "description": "External interrupt capability" }, { "description": "Internal Oscillators XTAL1 and XTAL2", "requires": [ { "function": "XTAL1", "count": 1 }, { "count": 1, "function": "XTAL2" } ], "protocol": { "role": [ "master" ], "type": "oscillators" }, "name": "Oscillators", "id": "oscillators" }, { "protocol": { "role": [ "clock_consumer" ], "type": "clock_input" }, "name": "Clock Input", "id": "clock_input", "requires": [ { "function": "CLKI", "count": 1 } ], "description": "Clock input pin" }, { "description": "Clock output pin", "protocol": { "role": [ "clock_provider" ], "type": "clock_output" }, "name": "Clock Output", "id": "clock_output", "requires": [ { "count": 1, "function": "CLKO" } ] }, { "requires": [ { "function": "AREF", "count": 1 } ], "protocol": { "role": [ "master" ], "type": "adc_reference" }, "name": "ADC Reference", "id": "adc_reference", "description": "ADC reference voltage pins" }, { "name": "Timer", "id": "timer", "protocol": { "role": [ "master" ], "type": "timer" }, "requires": [ { "count": 1, "function": "T0" } ], "description": "Timer/Counter" } ], "resources": [ { "logic_levels": { "v_il_max_V": 1, "v_ih_min_V": 4.5 }, "has_internal_pulldown": false, "description": "PCINT5 / !RESET / ADC0 / dW", "name": "Pin 1", "power_domain_id": "vcc", "id": "pb5", "current_rating": { "sink": { "max_continuous_mA": 40 }, "source": { "max_continuous_mA": 40 } }, "has_internal_pullup": true, "connector_type": "through_hole", "functions": [ { "shareable_with": [], "name": "Pin Change Interrupt", "description": "PCINT5 pin-change interrupt source. Only available when the RSTDISBL fuse repurposes the pin as PB5; latches on any logic-level transition on the pin.", "signal_class": "data", "direction": "sink" }, { "direction": "sink", "description": "Active-low external reset input (default function). Holds the AVR core in reset while driven low; minimum recognised pulse width is 2.5 us. Internal pull-up is enabled at power-up.", "signal_class": "data", "shareable_with": [], "name": "Reset" }, { "shareable_with": [], "name": "ADC", "description": "ADC0 single-ended 10-bit analog input channel. Selectable only after the RSTDISBL fuse turns the pin into general-purpose PB5.", "signal_class": "sense", "direction": "sink" }, { "direction": "bidirectional", "description": "debugWIRE single-wire on-chip debug interface, multiplexed on the RESET pin when the DWEN fuse is programmed. Replaces conventional ISP behaviour.", "signal_class": "data", "shareable_with": [], "name": "Debug" } ], "notes": "RESET is the default function and uses a tighter threshold than regular GPIO: V_IH min = 0.9*VCC, V_IL max = 0.2*VCC (values shown at VCC=5 V). Programming the RSTDISBL fuse to free PB5 as GPIO/ADC0/PCINT5 permanently disables ISP programming — recovery requires a high-voltage serial programmer. The high-voltage programming mode tolerates up to +13 V on this pin only." }, { "logic_levels": { "v_ol_max_V": 0.6, "v_il_max_V": 1.5, "v_oh_min_V": 4.3, "v_ih_min_V": 3 }, "has_internal_pulldown": false, "description": "PCINT3 / XTAL1 / CLKI / !OC1B / ADC3", "name": "Pin 2", "power_domain_id": "vcc", "notes": "Standard GPIO thresholds at VCC=5 V: V_IH min = 0.6*VCC, V_IL max = 0.3*VCC; V_OH min = 4.3 V at 10 mA source, V_OL max = 0.6 V at 10 mA sink. When PB3 is committed to XTAL1/CLKI the pin cannot also act as a GPIO, PWM, or ADC channel — the crystal load capacitors occupy the net.", "current_rating": { "sink": { "max_continuous_mA": 40 }, "source": { "max_continuous_mA": 40 } }, "has_internal_pullup": true, "connector_type": "through_hole", "functions": [ { "direction": "sink", "description": "PCINT3 pin-change interrupt source. Fires on any logic-level transition on PB3.", "signal_class": "data", "shareable_with": [], "name": "Pin Change Interrupt" }, { "direction": "sink", "description": "Crystal oscillator input. Pairs with XTAL2 on PB4 to drive an external 0-20 MHz crystal/resonator when the CKSEL fuses select the low/high-frequency crystal source. Pin is unavailable for other duties while the crystal oscillator is enabled.", "signal_class": "clock", "shareable_with": [], "name": "XTAL1" }, { "direction": "sink", "description": "External clock input. Routes a single-ended logic-level clock straight into the AVR core when the CKSEL fuses select the external-clock source. Mutually exclusive with XTAL1 crystal mode.", "signal_class": "clock", "shareable_with": [], "name": "CLKI" }, { "description": "Timer1 compare-match output OC1B (inverted). Capable of high-speed PWM up to ~250 kHz at 8-bit resolution when fed from the internal 64 MHz PLL clock.", "signal_class": "data", "direction": "source", "shareable_with": [], "name": "!PWM" }, { "direction": "sink", "description": "ADC3 single-ended 10-bit analog input channel.", "signal_class": "sense", "shareable_with": [], "name": "ADC" } ], "id": "pb3" }, { "power_domain_id": "vcc", "id": "pb4", "current_rating": { "source": { "max_continuous_mA": 40 }, "sink": { "max_continuous_mA": 40 } }, "has_internal_pullup": true, "connector_type": "through_hole", "functions": [ { "shareable_with": [], "name": "Pin Change Interrupt", "direction": "sink", "description": "PCINT4 pin-change interrupt source. Fires on any logic-level transition on PB4.", "signal_class": "data" }, { "direction": "source", "description": "Crystal oscillator output. Pairs with XTAL1 on PB3 to drive an external crystal/resonator when the CKSEL fuses select a crystal source.", "signal_class": "clock", "shareable_with": [], "name": "XTAL2" }, { "description": "Buffered system clock output. Enabled by programming the CKOUT fuse; outputs the divided system clock so downstream devices can be slaved to the AVR.", "signal_class": "clock", "direction": "source", "shareable_with": [], "name": "CLKO" }, { "shareable_with": [], "name": "PWM", "direction": "source", "description": "Timer1 compare-match output OC1B. Capable of high-speed PWM up to ~250 kHz at 8-bit resolution when fed from the internal 64 MHz PLL clock.", "signal_class": "data" }, { "description": "ADC2 single-ended 10-bit analog input channel.", "signal_class": "sense", "direction": "sink", "shareable_with": [], "name": "ADC" } ], "notes": "Standard GPIO thresholds at VCC=5 V: V_IH min = 0.6*VCC, V_IL max = 0.3*VCC; V_OH min = 4.3 V at 10 mA source, V_OL max = 0.6 V at 10 mA sink. When PB4 is committed to XTAL2 the pin cannot also act as GPIO, PWM, or ADC.", "logic_levels": { "v_oh_min_V": 4.3, "v_ih_min_V": 3, "v_ol_max_V": 0.6, "v_il_max_V": 1.5 }, "has_internal_pulldown": false, "description": "PCINT4/ XTAL2/ CLKO / OC1B / ADC2", "name": "Pin 5" }, { "id": "gnd", "current_rating": { "sink": { "max_continuous_mA": 200 } }, "has_internal_pullup": false, "connector_type": "through_hole", "functions": [ { "shareable_with": [], "name": "GND", "direction": "sink", "description": "Common ground return for the AVR core and the I/O pad ring. Reference for all VCC, signal, and ADC measurements.", "signal_class": "ground" } ], "notes": "Total continuous return current through the GND pin is limited to 200 mA (same absolute-max as the VCC pin). Single-pin ground — place the decoupling capacitor between this pin and the VCC pin with the shortest possible loop.", "power_domain_id": "vcc", "name": "Pin 8", "has_internal_pulldown": false, "description": "GND" }, { "power_domain_id": "vcc", "current_rating": { "source": { "max_continuous_mA": 40 }, "sink": { "max_continuous_mA": 40 } }, "has_internal_pullup": true, "connector_type": "through_hole", "functions": [ { "shareable_with": [], "name": "MOSI", "direction": "bidirectional", "description": "SPI master-out/slave-in data line used by AVR ISP programmers (slave role on this device, sinking writes; mastered out when USI is configured as SPI master).", "signal_class": "data" }, { "shareable_with": [], "name": "DI", "description": "USI serial data input. Sampled in three-wire (SPI-like) and two-wire (I2C-like) USI modes.", "signal_class": "data", "direction": "sink" }, { "shareable_with": [], "name": "SDA", "direction": "bidirectional", "description": "USI two-wire (I2C-compatible) data line. Open-drain when driven low; idle state must be pulled high externally.", "signal_class": "data" }, { "description": "Analog comparator positive input.", "signal_class": "sense", "direction": "sink", "shareable_with": [], "name": "AIN0" }, { "description": "Timer0 compare-match output OC0A — 8-bit PWM up to ~62 kHz at the typical 16 MHz system clock.", "signal_class": "data", "direction": "source", "shareable_with": [], "name": "PWM" }, { "shareable_with": [], "name": "!PWM", "direction": "source", "description": "Timer1 compare-match output OC1A (inverted). High-speed PWM up to ~250 kHz when the timer is fed from the 64 MHz PLL clock.", "signal_class": "data" }, { "direction": "sink", "description": "External ADC reference voltage input. Selected by the REFS bits in ADMUX; must lie between AGND and VCC.", "signal_class": "sense", "shareable_with": [], "name": "AREF" }, { "direction": "sink", "description": "PCINT0 pin-change interrupt source. Fires on any logic-level transition on PB0.", "signal_class": "data", "shareable_with": [], "name": "Pin Change Interrupt" } ], "id": "pb0", "notes": "Standard GPIO thresholds at VCC=5 V: V_IH min = 0.6*VCC, V_IL max = 0.3*VCC; V_OH min = 4.3 V at 10 mA source, V_OL max = 0.6 V at 10 mA sink. USI SDA on this pin is open-drain and needs an external pull-up (typically 4.7 kΩ at 100 kHz or 2.2 kΩ at 400 kHz). The pin also doubles as the AREF input and as the ISP MOSI line — isolate during programming if it is also driving a peripheral net.", "logic_levels": { "v_oh_min_V": 4.3, "v_ih_min_V": 3, "v_il_max_V": 1.5, "v_ol_max_V": 0.6 }, "has_internal_pulldown": false, "description": "MOSI / DI / SDA / AIN0 / OC0A / !OC1A / AREF / PCINT0", "name": "Pin 11" }, { "power_domain_id": "vcc", "id": "pb1", "current_rating": { "source": { "max_continuous_mA": 40 }, "sink": { "max_continuous_mA": 40 } }, "has_internal_pullup": true, "connector_type": "through_hole", "functions": [ { "direction": "bidirectional", "description": "SPI master-in/slave-out data line used by AVR ISP programmers (source role on this device when reading flash; sink when USI is configured as SPI master).", "signal_class": "data", "shareable_with": [], "name": "MISO" }, { "description": "USI serial data output. Driven in three-wire (SPI-like) USI modes.", "signal_class": "data", "direction": "source", "shareable_with": [], "name": "DO" }, { "direction": "sink", "description": "Analog comparator negative input.", "signal_class": "sense", "shareable_with": [], "name": "AIN1" }, { "description": "Timer0 compare-match output OC0B (8-bit, up to ~62 kHz) and Timer1 compare-match output OC1A — high-speed PWM up to ~250 kHz when Timer1 is fed from the 64 MHz PLL clock.", "signal_class": "data", "direction": "source", "shareable_with": [], "name": "PWM" }, { "shareable_with": [], "name": "Pin Change Interrupt", "direction": "sink", "description": "PCINT1 pin-change interrupt source. Fires on any logic-level transition on PB1.", "signal_class": "data" } ], "notes": "Standard GPIO thresholds at VCC=5 V: V_IH min = 0.6*VCC, V_IL max = 0.3*VCC; V_OH min = 4.3 V at 10 mA source, V_OL max = 0.6 V at 10 mA sink. This pin is the only ATtiny85 GPIO that lacks an ADC channel — assign PB1 to digital/USI/PWM duties when possible and keep PB2/PB3/PB4 free for ADC.", "logic_levels": { "v_oh_min_V": 4.3, "v_ih_min_V": 3, "v_il_max_V": 1.5, "v_ol_max_V": 0.6 }, "has_internal_pulldown": false, "description": "MISO / DO / AIN1 / OC0B / OC1A / PCINT1", "name": "Pin 12" }, { "id": "pb2", "current_rating": { "sink": { "max_continuous_mA": 40 }, "source": { "max_continuous_mA": 40 } }, "has_internal_pullup": true, "connector_type": "through_hole", "functions": [ { "direction": "bidirectional", "description": "SPI serial clock line. Sourced by the AVR ISP programmer during programming; sourced or sunk by USI depending on master/slave configuration.", "signal_class": "clock", "shareable_with": [], "name": "SCK" }, { "shareable_with": [], "name": "USCK", "direction": "bidirectional", "description": "USI serial clock. Driven when USI is configured as master; sampled when USI is slave.", "signal_class": "clock" }, { "direction": "bidirectional", "description": "USI two-wire (I2C-compatible) clock line. Open-drain when driven low; idle state must be pulled high externally.", "signal_class": "clock", "shareable_with": [], "name": "SCL" }, { "shareable_with": [], "name": "ADC", "direction": "sink", "description": "ADC1 single-ended 10-bit analog input channel.", "signal_class": "sense" }, { "shareable_with": [], "name": "T0", "direction": "sink", "description": "Timer/Counter0 external clock input. Counts rising or falling edges per the CS02:0 bits.", "signal_class": "clock" }, { "direction": "sink", "description": "INT0 dedicated external interrupt input. Triggers on low level or on rising/falling/any edge per the ISC01:0 bits — the only edge-configurable external interrupt on the device.", "signal_class": "data", "shareable_with": [], "name": "Interrupt" }, { "direction": "sink", "description": "PCINT2 pin-change interrupt source. Fires on any logic-level transition on PB2.", "signal_class": "data", "shareable_with": [], "name": "Pin Change Interrupt" } ], "notes": "Standard GPIO thresholds at VCC=5 V: V_IH min = 0.6*VCC, V_IL max = 0.3*VCC; V_OH min = 4.3 V at 10 mA source, V_OL max = 0.6 V at 10 mA sink. USI SCL is open-drain and needs an external pull-up (typically 4.7 kΩ at 100 kHz or 2.2 kΩ at 400 kHz). INT0 — the only edge-configurable external interrupt on the device — is unique to this pin. PB2 also doubles as the ISP SCK line — isolate during programming if it is also driving a peripheral net.", "power_domain_id": "vcc", "name": "Pin 14", "logic_levels": { "v_oh_min_V": 4.3, "v_ih_min_V": 3, "v_ol_max_V": 0.6, "v_il_max_V": 1.5 }, "has_internal_pulldown": false, "description": "SCK / USCK / SCL / ADC1 / T0 / INT0 / PCINT2" }, { "name": "Pin 15", "has_internal_pulldown": false, "description": "VCC", "notes": "Single-rail supply for both the AVR core and the I/O pad ring. Absolute-max supply voltage is 6.0 V — exceeding it damages the part. Total continuous current through the VCC pin is limited to 200 mA, which also caps the sum of per-pin source currents.", "current_rating": { "sink": { "max_continuous_mA": 200 } }, "has_internal_pullup": false, "connector_type": "through_hole", "functions": [ { "description": "Positive supply input. 2.7-5.5 V for operation up to 10 MHz; 4.5-5.5 V for the 20 MHz speed grade. Decouple with a 100 nF ceramic capacitor close to the pin.", "signal_class": "power", "direction": "sink", "shareable_with": [], "name": "VCC" } ], "id": "vcc", "power_domain_id": "vcc" } ], "metadata": { "absolute_maximum_ratings": { "operating_temperature_absmax_C": [ -55, 125 ], "pin_voltage_V_non_reset": [ -0.5, "VCC + 0.5" ], "supply_voltage_V": [ -0.5, 6 ], "pin_voltage_V_reset": [ -0.5, 13 ], "vcc_or_gnd_continuous_current_mA": 200, "junction_temperature_C": 150, "storage_temperature_C": [ -65, 150 ], "pin_continuous_current_mA": 40 }, "sram_memory_B": 512, "active_current_typ": { "at_5V_20MHz_mA": 9, "at_5V_8MHz_mA": 5, "at_3V_4MHz_mA": 1.5, "at_1p8V_1MHz_mA": 0.3 }, "package_type": "PDIP-8", "pwm_channels": 4, "adc_channels": 4, "max_total_vcc_or_gnd_current_mA": 200, "eeprom_memory_B": 512, "flash_memory_KB": 8, "sleep_modes": [ "idle", "adc_noise_reduction", "power_down" ], "eeprom_endurance_cycles": 100000, "flash_endurance_cycles": 10000, "pll_peripheral_clock_MHz": 64, "timer_count": 2, "gpio_count": 6, "architecture": "8-bit AVR RISC", "logic_thresholds_V": { "v_oh_min_V_at_5V_10mA_source": 4.3, "v_il_max_fraction_vcc": 0.3, "v_ol_max_V_at_5V_10mA_sink": 0.6, "v_ih_min_fraction_vcc": 0.6 }, "max_clock_speed_MHz": { "at_4p5V_to_5p5V": 20, "at_2p7V_to_5p5V": 10 }, "comparator_count": 1, "programming_interfaces": [ "spi_isp_6pin", "debugwire", "high_voltage_serial_programming" ], "adc_resolution_bits": 10, "instruction_set": "AVR (120 instructions)", "internal_oscillators_MHz": [ 8, 0.128 ], "power_down_current_typ_uA": { "at_1p8V_wdt_off": 0.1, "at_5V_wdt_off": 0.5 }, "max_pin_current_mA": 40, "pin_names": [] }, "domain": "electrical" }, { "resources": [ { "notes": "Footprint-only mounting pin in the 20-pin layout; no electrical net inside the PDIP-8 package.", "name": "Pin 3", "id": "pin_3", "functions": [ { "shareable_with": [], "name": "DNC", "description": "Do not connect. Footprint mounting pin only; no internal bond to the PDIP-8 die." } ], "connector_type": "through_hole", "description": "DNC Mounting Pin 3" }, { "description": "DNC Mounting Pin 4", "notes": "Footprint-only mounting pin in the 20-pin layout; no electrical net inside the PDIP-8 package.", "functions": [ { "description": "Do not connect. Footprint mounting pin only; no internal bond to the PDIP-8 die.", "shareable_with": [], "name": "DNC" } ], "connector_type": "through_hole", "name": "Pin 4", "id": "pin_4" }, { "description": "DNC Mounting Pin 6", "functions": [ { "shareable_with": [], "name": "DNC", "description": "Do not connect. Footprint mounting pin only; no internal bond to the PDIP-8 die." } ], "connector_type": "through_hole", "name": "Pin 6", "id": "pin_6", "notes": "Footprint-only mounting pin in the 20-pin layout; no electrical net inside the PDIP-8 package." }, { "functions": [ { "description": "Do not connect. Footprint mounting pin only; no internal bond to the PDIP-8 die.", "shareable_with": [], "name": "DNC" } ], "connector_type": "through_hole", "name": "Pin 7", "id": "pin_7", "notes": "Footprint-only mounting pin in the 20-pin layout; no electrical net inside the PDIP-8 package.", "description": "DNC Mounting Pin 7" }, { "description": "DNC Mounting Pin 9", "notes": "Footprint-only mounting pin in the 20-pin layout; no electrical net inside the PDIP-8 package.", "functions": [ { "description": "Do not connect. Footprint mounting pin only; no internal bond to the PDIP-8 die.", "shareable_with": [], "name": "DNC" } ], "connector_type": "through_hole", "name": "Pin 9", "id": "pin_9" }, { "functions": [ { "shareable_with": [], "name": "DNC", "description": "Do not connect. Footprint mounting pin only; no internal bond to the PDIP-8 die." } ], "connector_type": "through_hole", "name": "Pin 10", "id": "pin_10", "notes": "Footprint-only mounting pin in the 20-pin layout; no electrical net inside the PDIP-8 package.", "description": "DNC Mounting Pin 10" }, { "notes": "Footprint-only mounting pin in the 20-pin layout; no electrical net inside the PDIP-8 package.", "functions": [ { "description": "Do not connect. Footprint mounting pin only; no internal bond to the PDIP-8 die.", "shareable_with": [], "name": "DNC" } ], "connector_type": "through_hole", "name": "Pin 13", "id": "pin_13", "description": "DNC Mounting Pin 13" }, { "functions": [ { "description": "Do not connect. Footprint mounting pin only; no internal bond to the PDIP-8 die.", "shareable_with": [], "name": "DNC" } ], "connector_type": "through_hole", "name": "Pin 16", "id": "pin_16", "notes": "Footprint-only mounting pin in the 20-pin layout; no electrical net inside the PDIP-8 package.", "description": "DNC Mounting Pin 16" }, { "notes": "Footprint-only mounting pin in the 20-pin layout; no electrical net inside the PDIP-8 package.", "functions": [ { "shareable_with": [], "name": "DNC", "description": "Do not connect. Footprint mounting pin only; no internal bond to the PDIP-8 die." } ], "connector_type": "through_hole", "name": "Pin 17", "id": "pin_17", "description": "DNC Mounting Pin 17" }, { "notes": "Footprint-only mounting pin in the 20-pin layout; no electrical net inside the PDIP-8 package.", "name": "Pin 18", "id": "pin_18", "functions": [ { "shareable_with": [], "name": "DNC", "description": "Do not connect. Footprint mounting pin only; no internal bond to the PDIP-8 die." } ], "connector_type": "through_hole", "description": "DNC Mounting Pin 18" }, { "functions": [ { "shareable_with": [], "name": "DNC", "description": "Do not connect. Footprint mounting pin only; no internal bond to the PDIP-8 die." } ], "connector_type": "through_hole", "name": "Pin 19", "id": "pin_19", "notes": "Footprint-only mounting pin in the 20-pin layout; no electrical net inside the PDIP-8 package.", "description": "DNC Mounting Pin 19" }, { "description": "DNC Mounting Pin 20", "notes": "Footprint-only mounting pin in the 20-pin layout; no electrical net inside the PDIP-8 package.", "name": "Pin 20", "id": "pin_20", "functions": [ { "shareable_with": [], "name": "DNC", "description": "Do not connect. Footprint mounting pin only; no internal bond to the PDIP-8 die." } ], "connector_type": "through_hole" } ], "weight_g": 0.55, "interfaces": [ { "protocol": { "role": "mounting_point", "type": "mechanical_connection" }, "name": "DNC Mounting Pins", "id": "dnc", "requires": [ { "function": "DNC", "count": 1 } ], "description": "DNC Mounting Pins 3, 4, 6, 7, 9, 10, 13, 16-20", "max_instances": 12 } ], "dimensions_mm": { "height": 4.32, "length": 9.43, "width": 7.94 }, "metadata": { "field_serviceable": true, "mounting_method": "through_hole", "requires_special_tools": false }, "package_type": "PDIP-8", "domain": "mechanical" }, { "interfaces": [], "operating_temperature_C": [ -40, 85 ], "resources": [], "metadata": { "thermal_monitoring_available": false, "requires_thermal_management": false }, "domain": "thermal" } ], "artifacts": [ { "type": "datasheet", "url": "https://ww1.microchip.com/downloads/en/devicedoc/atmel-2586-avr-8-bit-microcontroller-attiny25-attiny45-attiny85_datasheet.pdf", "name": "ATtiny25/45/85 Datasheet (Atmel-2586)", "id": "art_datasheet" }, { "name": "ATtiny85 Microchip product page", "id": "art_product_page", "url": "https://www.microchip.com/en-us/product/attiny85", "type": "link" }, { "size": 21257, "name": "ATTINY85-20PU product photo (DigiKey)", "id": "art_product_image", "mimeType": "image/jpeg", "storagePath": "protoparts/attiny85/artifacts/art_product_image.jpg", "url": "https://storage.googleapis.com/protoboard-delta.firebasestorage.app/protoparts/attiny85/artifacts/art_product_image.jpg", "type": "image" }, { "name": "Microchip ATtiny85 8-bit AVR Microcontroller thumbnail", "id": "art_thumbnail", "url": "https://storage.googleapis.com/protoboard-delta.firebasestorage.app/protoparts/attiny85/thumbnail.png", "type": "image" } ], "previewArtifactId": "art_thumbnail", "application_examples": [ "Compact embedded controller for sensor reading and small actuator control where 6 GPIO are sufficient.", "Arduino-compatible projects programmed via Digispark-style USB bootloader or 6-pin ISP using ATTinyCore.", "Low-power battery-operated nodes leveraging the power-down sleep mode and watchdog wake-up.", "USI-driven I2C master for adding extra peripherals to a board that has no spare hardware I2C.", "High-speed PWM generation (up to ~250 kHz) on Timer1 using the internal 64 MHz PLL clock source." ], "metadata": { "type": "microcontroller", "schema_version": "1.5.0", "thumbnail": "https://storage.googleapis.com/protoboard-delta.firebasestorage.app/protoparts/attiny85/thumbnail.png", "taxonomy": [ "microcontroller" ], "id": "ATTINY85-20SU", "tags": [ "attiny85", "attiny", "avr", "microcontroller", "mcu", "8-bit", "atmel", "microchip", "pdip-8", "dip-8", "usi", "arduino-compatible" ], "manufacturer": "Microchip Technology (Atmel)", "version": "1.0", "part_number": "ATTINY85-20PU", "name": "Microchip ATtiny85 8-bit AVR Microcontroller", "description": "Microchip (formerly Atmel) ATtiny85 8-bit AVR RISC microcontroller IC with 8 KB flash, 512 B EEPROM, 512 B SRAM, six GPIO, 4-channel 10-bit ADC, Universal Serial Interface (USI) supporting SPI/I2C-like signalling, two 8-bit timer/counters with PWM, internal RC oscillator, and an internal PLL for 64 MHz high-speed PWM. Default variant: ATTINY85-20PU in 8-pin PDIP, rated to 20 MHz at 4.5-5.5 V, -40 to +85 C industrial temperature range. Programmed via 6-pin AVR ISP (SPI on PB0/PB1/PB2 plus RESET) or debugWIRE single-wire interface on the RESET pin.", "datasheet_url": "https://ww1.microchip.com/downloads/en/devicedoc/atmel-2586-avr-8-bit-microcontroller-attiny25-attiny45-attiny85_datasheet.pdf" }, "usage_notes": "The ATtiny85 is the largest member of the ATtiny25/45/85 family. Pin assignments are identical across the three; only flash and SRAM capacity differ. When used in a 4.5-5.5 V system with the internal 8 MHz RC oscillator the chip can be powered directly from the supply with only a decoupling capacitor; no external crystal is required for most applications. The Universal Serial Interface (USI) is shared between SPI and TWI/I2C modes — only one protocol can be active at a time. ISP programming reuses the same three USI pins, so an ISP header on a board running USI peripherals needs to share or isolate those nets during programming. The RESET pin can be reclaimed as PB5 by programming the RSTDISBL fuse, but this disables conventional ISP programming and you will then need a high-voltage serial programmer to recover the chip.", "design_rules": [ "Place a 0.1 uF (100 nF) ceramic decoupling capacitor between VCC (pin 8) and GND (pin 4) as close to the package as possible.", "If the RESET pin (PB5, pin 1) is left in its default reset role, pull it to VCC through a 10 kΩ resistor and bring it out to a reset button or programming header. Do not leave RESET floating in noisy environments.", "For ISP programming, expose PB0 (MOSI), PB1 (MISO), PB2 (SCK), RESET, VCC, and GND on a standard 6-pin AVR ISP header.", "When using USI as an I2C/TWI master or slave, add external pull-ups on SDA (PB0) and SCL (PB2): typically 4.7 kΩ at 100 kHz, 2.2 kΩ at 400 kHz.", "Do not sink or source more than 40 mA on a single pin, and keep the sum of all currents through VCC or GND below 200 mA. Use an external transistor or driver for higher-current loads.", "If using PB3/PB4 as a crystal oscillator (XTAL1/XTAL2), they cannot also drive PWM, ADC, or GPIO — the crystal load capacitors and physical crystal occupy the pins.", "The internal 8 MHz RC oscillator drifts up to ±10% over voltage and temperature; for UART or other timing-sensitive bit-banged protocols, calibrate OSCCAL or use an external crystal." ] }